XMSS and Embedded Systems. XMSS Hardware Accelerators for RISC-V: Published on Cryptology ePrint Archive

AuthorWang, Wen; Jungk, Bernhard; Wälde, Julian; Deng, Shuwen; Gupta, Naina; Szefer, Jakub; Niederhagen, Ruben
TypePreprint, Electronic Publication, Paper
AbstractWe describe a software-hardware co-design for the hash-based post-quantum signature scheme XMSS on a RISC-V embedded processor. We provide software optimizations for the XMSS reference implementation for SHA-256 parameter sets and several hardware accelerators that allow to balance area usage and performance based on individual needs. By integrating our hardware accelerators into the RISC-V processor, the version with the best time-area product generates a key pair (that can be used to generate 210 signatures) in 3.44s achieving an over 54x speedup in wall-clock time compared to the pure software version. For such a key pair, signature generation takes less than 10 ms and verification takes less than 6 ms, bringing speedups of over 42x and 17x respectively. This shows that embedded systems equipped with scheme-specific hardware accelerators are able to practically use XMSS. We tested and measured the cycle count of our implementation on an Intel Cyclone V SoC FPGA. The integration of our XMSS accelerators into an embedded RISC-V processor shows that it is possible to use hash-based post-quantum signatures for a large variety of embedded applications.
SerieCryptology ePrint Archive. Report 2018/1225