Publications

Author	Wang, Meizhi; Chen, Yi-Ru; Nibhanupudi, S.S. Teja; Amini, Elham; Saavedra, Antonio; Wang, Yinan; Wasserman, Daniel; Seifert, Jean-Pierre; Kulkarni, Jaydeep P.
Date	2025
Type	Conference Paper
Abstract	Photon Emission (PE) from Integrated Circuits (IC) is an emerging non-invasive side channel that poses a serious security risk to modern System-on-Chips (SoCs). These emissions, generated during transistor switching, are determined by circuit operations and can be exploited in Side-Channel Analysis (SCA). Furthermore, physical design choices, such as standard cell placement and routing, affect how these emissions propagate and are detected. This makes it crucial to assess and mitigate such risks during the design phase. This paper presents a novel photonic side-channel analysis framework that integrates directly into the physical design flow. The framework enables designers to assess security vulnerabilities in digital ASIC designs by generating both time-resolved and accumulated PE maps at the standard-cell gate level. These PE maps can be applied to various side-channel analysis methods to identify vulnerable regions in the circuit. We demonstrate the framework by applying it to a 40nm 128-bit Advanced Encryption Standard (AES) core, where we employ localized Correlation PE Attacks (CPEA) on simulated time-resolved PE maps. This approach pinpoints regions with high side-channel leakage. The results showcase the framework’s effectiveness in providing early detection and allow designers to enhance the overall security of the design against PE-related vulnerabilities. To validate our simulation framework, we compared the simulated accumulated PE maps with real-world measurements from a 40nm AES test chip. The close alignment between simulated and measured data confirms the accuracy of our simulator in predicting photon emission behavior across the chip.
Conference	International Symposium on Physical Design 2025
Url	https://publica.fraunhofer.de/handle/publica/509168