Abstract

Implementing cryptographic functions securely in the presence of physical adversaries is still a challenge although a lion's share of research in the physical security domain has been put in development of countermeasures. Among several protection schemes, masking has absorbed the most attention of researchers in both academic and industrial communities. This is due to its theoretical foundation allowing to provide proofs, and model the achieved security level. In return, masking schemes are difficult to realize as the implementation process often is manual, complex, and error-prone, and requires a high level of expertise. This motivated the need for tools that allow the designers and engineers to evaluate as well as generate masked (protected) implementations through an automated fashion. 

In this talk, in addition to the basics of hardware masking, a set of tools are presented, which supports developers in the process of designing secure hardware circuits. The toolbox enables (1) fully automated protection of insecure circuits against side-channel analysis attacks and (2) efficient verification of their SCA resistance. As a result, circuits dealing with sensitive data can be reliably protected against such implementation attacks even by inexperienced engineers and developers.